MARC details
| 000 -LEADER |
|---|
| fixed length control field |
02759nam a2200265 a 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
39887 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
0000000000 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20240411192943.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
210120n s 000 0 eng d |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Lavagno, Luciano. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Electronic design automation for IC system design, verification, and testing |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc. |
Luciano Lavagno, Igor L. Makrov, Grant Martin, Louis K. Scheffer. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Boca Raton, Florida : |
| Name of publisher, distributor, etc. |
CRC Press, |
| Date of publication, distribution, etc. |
2016. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 online resource. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Includes bibliographical references. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
1: Overview -- 2: Integrated Circuit Design Process and Electronic Design Automation -- II: System-Level Design -- 3: Tools and Methodologies for System-Level Design -- 4: System-Level Specification and Modeling Languages -- 5: SoC Block-Based Design and IP Assembly -- 6: Performance Evaluation Methods for Multiprocessor System-on-Chip Designs -- 7: System-Level Power Management -- 8: Processor Modeling and Design Tools 9: Models and Tools for Complex Embedded Software and Systems -- 10: Using Performance Metrics to Select Microprocessor Cores for IC Designs -- 11: High-Level Synthesis -- III: Microarchitecture Design -- 12: Back-Annotating System-Level Models -- 13: Microarchitectural and System-Level Power Estimation and Optimization -- 14: Design Planning -- IV: Logic Verification -- 15: Design and Verification Languages -- 16: Digital Simulation -- 17: Leveraging Transaction-Level Models in an SoC Design Flow -- 18: Assertion-Based Verification -- 19: Hardware-Assisted Verification and Software Development 20: Formal Property Verification -- V: Test -- 21: Design-for-Test -- 22: Automatic Test Pattern Generation -- 23: Analog and Mixed-Signal Test. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
Electronic Design Automation for IC System Design, Verification, and Testing thoroughly examines system-level design, microarchitectural design, logic verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for integrated circuit (IC) designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits |
| General subdivision |
Computer-aided design. |
| Source of heading or term |
sears |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits |
| General subdivision |
Design and construction. |
| Source of heading or term |
sears |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits |
| General subdivision |
Testing. |
| Source of heading or term |
sears |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Makrov, Igor L. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Martin, Grant. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Scheffer, Louis K. |
| 856 ## - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
<a href="https://drive.google.com/file/d/1Pq74g8vRcO8eWCiDWKbzrKftDUGlFoAK/view?usp=sharing">https://drive.google.com/file/d/1Pq74g8vRcO8eWCiDWKbzrKftDUGlFoAK/view?usp=sharing</a> |
