Languages, design methods, and tools for electronic system design [electronic resource] : selected contributions from FDL 2016 / Franco Fummi, Robert Wille.

Includes bibliographical references and index.

Knowing Your AMS System's Limits: System Acceptance Region Exploration by Using Automated Model Refinement and Accelerated Simulation -- 1 Introduction -- 2 Related Work -- 3 Automated Model Refinement -- 4 Accelerated Analog Simulation Using Piecewise Linearization -- 4.1 Switching Between State-Space Models -- 4.2 Parallelizing the Specialized Root-Finding Algorithm -- 5 System Acceptance Regions -- 6 Application Scenario -- 7 Conclusion -- References -- Designing Reliable Cyber-Physical Systems -- 1 Introduction 2 Health Monitoring at the Analog/Mixed Signal Layer3 Comprehensive and Scalable RT-Level Reliability Analysis -- 3.1 Analysis Stage -- 3.2 Verification Stage -- 4 Qualification and Minimization of Concurrent Online Checkers -- 5 Managing Faults at SoC Level During In-Field Operation of CPS -- 5.1 Fault Management Infrastructure -- 5.2 Fault Classification and Handling -- 6 Many-Core Resource Management for Fault Tolerance -- 7 Deriving Adaptive Test Strategies from LTL-Specifications -- 8 Parameter Synthesis for CPS -- 8.1 Heuristics and Implementation 9 ConclusionsReferences -- On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation: A Case Study -- 1 Introduction -- 2 Related Work -- 3 Preliminaries -- 3.1 Interrupt Controller for Multiple Processors (IRQMP) -- 3.2 Extended Intermediate Verification Language (XIVL) -- 4 RTL-to-TLM Fault Correspondence Analysis -- 4.1 Correspondence Analysis Overview and Algorithm -- 4.2 Example -- Method Overview -- Fault Correspondence 5 Formal Fault Localization Analysis5.1 Annotations -- 5.2 Symbolic Error Injection Logic -- 5.3 Testbench -- 6 Case Study -- 6.1 Experiments -- 7 Conclusion -- References -- Error-Based Metric for Cross-Layer Cut Determination -- 1 Introduction -- 1.1 Research Methodology and Contributions -- 2 The Proposed Method -- 2.1 Hierarchical Modelling and Selective Abstraction -- 3 Hierarchical Modelling in Order Graphs -- 3.1 Introducing Hierarchies -- 3.2 Order Graphs -- 3.3 Cross-Layer Cuts -- 4 Selective Abstraction 5 Background on Stochastic Modelling6 Case Study -- 6.1 Platform Description -- 6.2 Power Modelling -- 6.3 Experiment Setup -- 6.4 Characterisation Experiments -- 7 Models and Results -- 7.1 State-Space Analysis -- 7.2 Simulation Results -- 8 Conclusions -- References -- Feature-Based State Space Coverage Metric for Analog Circuit Verification -- 1 Introduction and Related Work -- 2 State Space Model Generation -- 2.1 Analog Transition System (ATS) -- 3 State Space Coverage -- 3.1 State Space Coverage Calculation -- 3.2 Path Planning.

This book brings together a selection of the best papers from the nineteenth edition of the Forum on specification and Design Languages Conference (FDL), which took place on September 14-16, 2016, in Bremen, Germany. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems. · Covers analog-mixed signal design techniques; · Includes descriptions of methods for reliable system design as well as fault localization; · Introduces stochastic methods for power modeling; · Covers design techniques for analog and adiabatic circuits.